ppc64: review the comment style in proto file

No more use C++ comment style
Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
Reviewed-by: Dmitry Safonov <dsafonov@virtuozzo.com>
Signed-off-by: Pavel Emelyanov <xemul@virtuozzo.com>

images/core-ppc64.proto

 syntax = "proto2";
 
 message user_ppc64_regs_entry {
-	// Following is the list of regiters starting at r0.
+	/* Following is the list of regiters starting at r0. */
 	repeated uint64 gpr		= 1;
 	required uint64 nip		= 2;
 	required uint64 msr		= 3;
@@ -14,30 +14,34 @@ message user_ppc64_regs_entry {
 }
 
 message user_ppc64_fpstate_entry {
-	// Following is the list of regiters starting at fpr0
+	/* Following is the list of regiters starting at fpr0 */
 	repeated uint64 fpregs 		= 1;
 }
 
 message user_ppc64_vrstate_entry {
-	// Altivec registers
-	// The vector registers are 128bit registers (VSR[32..63]).
-	// The following vregs entry will store first the high part then the
-	// low one:
-	// 	VR0 = vrregs[0] << 64 | vrregs[1];
-	// 	VR1 = vrregs[2] << 64 | vrregs[3];
-	// 	..
-	// The last entry stores in a 128bit field the VSCR which is a 32bit
-	// value returned by the kernel in a 128 field.
+	/*
+	 * Altivec registers
+	 * The vector registers are 128bit registers (VSR[32..63]).
+	 * The following vregs entry will store first the high part then the
+	 * low one:
+	 * 	VR0 = vrregs[0] << 64 | vrregs[1];
+	 * 	VR1 = vrregs[2] << 64 | vrregs[3];
+	 * 	..
+	 * The last entry stores in a 128bit field the VSCR which is a 32bit
+	 * value returned by the kernel in a 128 field.
+	 */
 	repeated uint64 vrregs		= 1;
 	required uint32	vrsave		= 2;
 }
 
 message user_ppc64_vsxstate_entry {
-	// VSX registers
-	// The vector-scale registers are 128bit registers (VSR[0..64]).
-	// Since there is an overlapping over the VSX registers by the FPR and
-	// the Altivec registers, only the lower part of the first 32 VSX
-	// registers have to be saved.
+	/*
+	 * VSX registers
+	 * The vector-scale registers are 128bit registers (VSR[0..64]).
+	 * Since there is an overlapping over the VSX registers by the FPR and
+	 * the Altivec registers, only the lower part of the first 32 VSX
+	 * registers have to be saved.
+	 */
 	repeated uint64 vsxregs		= 1;
 }