ppc64: handle transactional memory state

The Power 8 introduces the transactional memory (TM) operations (see
Power ISA 3.0 for details).

The support for the transactional memory operation during the
checkpoint and restart requires extended ptrace API provided by the
kernel 4.8.

When checkpointing a thread while a transactional memory operation is
in progress, the TM checkpointed state is checkpointed through the new
ptrace API. If these new APIs are not available, the checkpoint is
aborted and an explicit error is reported.

At restart time, the TM state is pushed on the stack frame to be
reloaded by the kernel when reading the stack frame.

Only suspended TM operation could be checkpointed since active one
will be aborted once a system call is made. Suspended operation will
be aborted as well, and the checkpointed thread is expected to handle
the TM failure as usual (retrying is a good option).
Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
Reviewed-by: Dmitry Safonov <dsafonov@virtuozzo.com>
Signed-off-by: Pavel Emelyanov <xemul@virtuozzo.com>

criu/arch/ppc64/include/asm/restorer.h

@@ -32,13 +32,7 @@
 struct rt_sigframe {
         /* sys_rt_sigreturn requires the ucontext be the first field */
         struct ucontext uc;
-#if 1
-	/*
-	 * XXX: Assuming that transactional is turned on by default in
-	 * most of the Linux distribution.
-	 */
-        struct ucontext uc_transact;
-#endif
+        struct ucontext uc_transact;  	/* Transactional state	 */
         unsigned long _unused[2];
         unsigned int tramp[TRAMP_SIZE];
         struct rt_siginfo *pinfo;

criu/arch/ppc64/restorer.c

@@ -9,6 +9,37 @@
 
 int restore_nonsigframe_gpregs(UserPpc64RegsEntry *r)
 {
+#define SPRN_TFHAR	128
+#define SPRN_TFIAR	129
+#define SPRN_TEXASR	130
+
+	if (r->has_tfhar) {
+		asm __volatile__ (
+			"ld	3, %[value]	;"
+			"mtspr	%[sprn],3	;"
+			: [value]"=m"(r->tfhar)
+			: [sprn]"i"(SPRN_TFHAR)
+			: "r3");
+	}
+
+	if (r->has_tfiar) {
+		asm __volatile__ (
+			"ld	3, %[value]	;"
+			"mtspr	%[sprn],3	;"
+			: [value]"=m"(r->tfiar)
+			: [sprn]"i"(SPRN_TFIAR)
+			: "r3");
+	}
+
+	if (r->has_texasr) {
+		asm __volatile__ (
+			"ld	3, %[value]	;"
+			"mtspr	%[sprn],3	;"
+			: [value]"=m"(r->texasr)
+			: [sprn]"i"(SPRN_TEXASR)
+			: "r3");
+	}
+
 	return 0;
 }
 

images/core-ppc64.proto

@@ -11,6 +11,10 @@ message user_ppc64_regs_entry {
 	required uint64 xer		= 7;
 	required uint64 ccr		= 8;
 	required uint64 trap		= 9;
+	/* For Transactional memory support since P8 */
+	optional uint64 texasr		= 10;
+	optional uint64 tfhar		= 11;
+	optional uint64 tfiar		= 12;
 }
 
 message user_ppc64_fpstate_entry {
@@ -45,10 +49,21 @@ message user_ppc64_vsxstate_entry {
 	repeated uint64 vsxregs		= 1;
 }
 
+/*
+ * Transactional memory operation's state
+ */
+message user_ppc64_tm_regs_entry {
+	required user_ppc64_regs_entry		gpregs 		= 1;
+	optional user_ppc64_fpstate_entry	fpstate		= 2;
+	optional user_ppc64_vrstate_entry	vrstate		= 3;
+	optional user_ppc64_vsxstate_entry	vsxstate	= 4;
+}
+
 message thread_info_ppc64 {
 	required uint64			 	clear_tid_addr	= 1;
 	required user_ppc64_regs_entry	 	gpregs		= 2;
 	optional user_ppc64_fpstate_entry 	fpstate		= 3;
 	optional user_ppc64_vrstate_entry	vrstate		= 4;
 	optional user_ppc64_vsxstate_entry	vsxstate	= 5;
+	optional user_ppc64_tm_regs_entry	tmstate		= 6;
 }