protobuf: added description of messages to store the AArch64 CPU state

These messages are constructed in the same spirit as ARM and x86 ones
except for two major points:

* general-purpose registers are stored in a variable-length array
  of uint64's: the architecture provides 32 general-purpose registers
  that makes it unfeasible to create a separate protobuf field
  for each of them since it requires a lot of "copy-paste" to convert
  between the struct pt_regs and protobuf message; the length of
  the array storing registers is to be checked by the architecture-
  dependent CRIU code;

* AArch64 FP/SIMD registers are 128 bit long while protobuf lacks
  the support for integers of this size; the FP/SIMD registers
  are stored in an array of uint64, two consecutive elements
  of the array represent a single FP/SIMD register.
Signed-off-by: Alexander Kartashov <alekskartashov@parallels.com>
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Pavel Emelyanov <xemul@parallels.com>

protobuf/Makefile

@@ -13,6 +13,7 @@ proto-obj-y	+= stats.o
 proto-obj-y	+= core.o
 proto-obj-y	+= core-x86.o
 proto-obj-y	+= core-arm.o
+proto-obj-y	+= core-aarch64.o
 proto-obj-y	+= inventory.o
 proto-obj-y	+= fdinfo.o
 proto-obj-y	+= fown.o

protobuf/core-aarch64.proto

+message user_aarch64_regs_entry {
+	repeated uint64 regs	= 1;
+	required uint64 sp	= 2;
+	required uint64 pc	= 3;
+	required uint64 pstate	= 4;
+}
+
+message user_aarch64_fpsimd_context_entry {
+	repeated uint64 vregs	= 1;
+	required uint32 fpsr	= 2;
+	required uint32 fpcr	= 3;
+}
+
+message thread_info_aarch64 {
+	required uint64			 		clear_tid_addr	= 1;
+	required uint64					tls		= 2;
+	required user_aarch64_regs_entry		gpregs		= 3;
+	required user_aarch64_fpsimd_context_entry	fpsimd		= 4;
+}

protobuf/core.proto

 import "core-x86.proto";
 import "core-arm.proto";
+import "core-aarch64.proto";
 
 import "rlimit.proto";
 
@@ -52,11 +53,13 @@ message core_entry {
 		UNKNOWN		= 0;
 		X86_64		= 1;
 		ARM             = 2;
+		AARCH64		= 3;
 	}
 
 	required march			mtype		= 1;
 	optional thread_info_x86	thread_info	= 2;
 	optional thread_info_arm	ti_arm		= 6;
+	optional thread_info_aarch64	ti_aarch64	= 8;
 
 	optional task_core_entry	tc		= 3;
 	optional task_kobj_ids_entry	ids		= 4;