Commit f0fb0bc9 authored by Cyrill Gorcunov's avatar Cyrill Gorcunov Committed by Andrei Vagin

x86: cpu -- Add image definitions for fpu frames

Signed-off-by: 's avatarCyrill Gorcunov <gorcunov@gmail.com>
Reviewed-by: 's avatarDmitry Safonov <0x7f454c46@gmail.com>
Signed-off-by: 's avatarAndrei Vagin <avagin@virtuozzo.com>
parent e319aaa0
...@@ -40,8 +40,29 @@ message user_x86_regs_entry { ...@@ -40,8 +40,29 @@ message user_x86_regs_entry {
} }
message user_x86_xsave_entry { message user_x86_xsave_entry {
/* standart xsave features */
required uint64 xstate_bv = 1; required uint64 xstate_bv = 1;
/* AVX components: 16x 256-bit ymm registers, hi 128 bits */
repeated uint32 ymmh_space = 2; repeated uint32 ymmh_space = 2;
/* MPX components */
repeated uint64 bndreg_state = 3;
repeated uint64 bndcsr_state = 4;
/* AVX512 components: k0-k7, ZMM_Hi256, Hi16_ZMM */
repeated uint64 opmask_reg = 5;
repeated uint64 zmm_upper = 6;
repeated uint64 hi16_zmm = 7;
/* Protected keys */
repeated uint32 pkru = 8;
/*
* Processor trace (PT) and hardware duty cycling (HDC)
* are supervisor state components and only managed by
* xsaves/xrstors on cpl=0, so ignore them.
*/
} }
message user_x86_fpregs_entry { message user_x86_fpregs_entry {
......
...@@ -15,6 +15,8 @@ message cpuinfo_x86_entry { ...@@ -15,6 +15,8 @@ message cpuinfo_x86_entry {
repeated uint32 capability = 6; repeated uint32 capability = 6;
optional string model_id = 7; optional string model_id = 7;
optional uint64 xfeatures_mask = 8;
} }
message cpuinfo_ppc64_entry { message cpuinfo_ppc64_entry {
......
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